Many semiconductor devices and integrated circuits are manufactured using photolithographic processes. Often in such processes, a circuit design is transferred from a photomask (sometimes called a reticle) to a semiconductor wafer by using an optical imaging scanner/stepper system (“scanner system”). High production yield and quality of the produced circuits relies not just on the precision of the scanner system but also on the quality of the photomask and semiconductor wafer being used. Although many error sources influence the quality of the photomask and semiconductor wafer, key among them is surface flatness and roughness of both the photomask and the semiconductor wafer.
The issue of surface flatness and roughness for photomasks and semiconductor wafers is important in both the near future, as conventional optical lithography is pushed to its physical limits (e.g., the diffraction limit), as well as for future unconventional lithographic processes that are needed to move beyond the limitations of conventional optical lithography. For example, extreme ultraviolet (EUV)/soft x-ray lithographic processes are being explored as one way of replacing or supplementing conventional optical lithography. In EUV/soft x-ray lithography, non-axially symmetric imaging layouts are frequently employed. Such non-axially symmetric imaging layouts place tight restrictions on error sources such as imaging aberrations, distortions and overlay errors that, in turn, increase the surface flatness and roughness requirements of the optical components (including the reticle) and the wafer into the range of nanometers.
Currently, surface polishing in the semiconductor industry is mainly achieved by chemical mechanical planarization/polishing (CMP). Due to technical limitations of this approach, it is likely limited in utility to fabricated devices that can tolerate peak-valley flatness excursions on the order of micrometers or slightly better. Moreover, CMP is a global polishing technique, meaning that an entire chip or wafer is typically polished at once. As such, CMP is known to generate a signature “global bow” and create new surface errors while minimizes others. Other available surface polishing methods (e.g., mechanical polishing, magneto-fluid, or ion beam bombardment methods, etc) are tedious and time consuming, and are not easily transferred to volume-level production environments.
Therefore, what is needed is an improved polishing method that does not suffer from the problems associated with chemical mechanical planarization/polishing while still providing acceptable throughput and high accuracy surface polishing.